most citedIn-Datacenter Performance Analysis of a Tensor Processing Unit

23 citations · 85 across the 6 of their papers we have counts for

collaborators

6 papers

cs.AR2021★ 2 cited

Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks

Amirali Boroumand, Saugata Ghose, Berkin Akin +5

Emerging edge computing platforms often contain machine learning (ML) accelerators that can accelerate inference for a wide range of neural network (NN) models. These models are de…

cs.AR2021★ 20 cited

Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models

Amirali Boroumand, Saugata Ghose, Berkin Akin +5

As the need for edge computing grows, many modern consumer devices now contain edge machine learning (ML) accelerators that can compute a wide range of neural network (NN) models w…

cs.LG2021★ 17 cited

Rethinking Co-design of Neural Architectures and Hardware Accelerators

Yanqi Zhou, Xuanyi Dong, Berkin Akin +7

Neural architectures and hardware accelerators have been two driving forces for the progress in deep learning. Previous works typically attempt to optimize hardware given a fixed m…

cs.LG2021★ 13 cited

Apollo: Transferable Architecture Exploration

Amir Yazdanbakhsh, Christof Angermueller, Berkin Akin +7

The looming end of Moore's Law and ascending use of deep learning drives the design of custom accelerators that are optimized for specific neural architectures. Architecture explor…

cs.LG2021★ 10 cited

An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks

Kiran Seshadri, Berkin Akin, James Laudon +2

Edge TPUs are a domain of accelerators for low-power, edge devices and are widely used in various Google products such as Coral and Pixel devices. In this paper, we first discuss t…

cs.AR2017★ 23 cited

In-Datacenter Performance Analysis of a Tensor Processing Unit

Norman P. Jouppi, Cliff Young, Nishant Patil +72

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Process…