2 papers
cs.AR2024
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona +3
As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values compr…
physics.ins-det2024
Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
Daniel Malagon, Gabriel Torrens, Jaume Segura +1
We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells S…