activity
20182026
most citedIntelligent Identification of Two-Dimensional Structure by Machine-Learning Optical Microscopy

85 citations · 143 across the 28 of their papers we have counts for

collaborators

30 papers

cs.AI2026

EcoVLA: Energy-Efficient Device-Edge Co-Inference for Vision-Language-Action Models under Real-Time Constraints

Ao Zhou, Bo Dai, Le Yu +5

Vision-Language-Action (VLA) models have emerged as a promising foundation for Embodied AI, but their high inference cost poses significant challenges for deployment in robotic sys…

cs.CL2026

Focus-dLLM: Accelerating Long-Context Diffusion LLM Inference via Confidence-Guided Context Focusing

Lingkun Long, Yushi Huang, Shihao Bai +4

Diffusion Large Language Models (dLLMs) deliver strong long-context processing capability in a non-autoregressive decoding paradigm. However, the considerable computational cost of…

cs.CR2025

RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering

Weitao Pan, Meng Dong, Zhiliang Qiu +3

Reverse engineering of gate-level netlist is critical for Hardware Trojans detection and Design Piracy counteracting. The primary task of gate-level reverse engineering is to separ…

cs.LG2025★ 2 cited

GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search

Ao Zhou, Jianlei Yang, Tong Qiao +4

Graph Neural Networks (GNNs) have emerged as the state-of-the-art graph learning method. However, achieving efficient GNN inference on edge devices poses significant challenges, li…

cs.AR2025

CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures

Yingjie Qi, Jianlei Yang, Rubing Yang +5

Compute-in-memory (CIM) has emerged as a pivotal direction for accelerating workloads in the field of machine learning, such as Deep Neural Networks (DNNs). However, the effective…

cs.AR2025

MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator

Xiaolin He, Cenlin Duan, Yingjie Qi +2

Computing-in-Memory (CIM) architectures have emerged as a promising solution for accelerating Deep Neural Networks (DNNs) by mitigating data movement bottlenecks. However, realizin…

cs.DC2025

ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments

Ao Zhou, Jianlei Yang, Tong Qiao +5

The device-edge co-inference paradigm effectively bridges the gap between the high resource demands of Graph Neural Networks (GNNs) and limited device resources, making it a promis…

cs.DC2025

Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms

Tong Qiao, Ao Zhou, Yingjie Qi +4

Graph Neural Networks (GNNs) have been widely adopted due to their strong performance. However, GNN training often relies on expensive, high-performance computing platforms, limiti…

cs.AR2025★ 2 cited

Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design

Tianwei Pan, Tianao Dai, Jianlei Yang +6

Pairing-based cryptography (PBC) is crucial in modern cryptographic applications. With the rapid advancement of adversarial research and the growing diversity of application requir…

cs.AR2025

HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference

Cenlin Duan, Jianlei Yang, Rubing Yang +8

The deployment of large language models (LLMs) presents significant challenges due to their enormous memory footprints, low arithmetic intensity, and stringent latency requirements…

cs.CL2025

SlimInfer: Accelerating Long-Context LLM Inference via Dynamic Token Pruning

Lingkun Long, Rubing Yang, Yushi Huang +3

Long-context inference for Large Language Models (LLMs) is heavily limited by high computational demands. While several existing methods optimize attention computation, they still…

cs.AR2025

Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity

Cenlin Duan, Jianlei Yang, Yikun Wang +7

Processing-in-memory (PIM) is a transformative architectural paradigm designed to overcome the Von Neumann bottleneck. Among PIM architectures, digital SRAM-PIM emerges as a promis…

cs.AR2025

CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures

Yingjie Qi, Jianlei Yang, Yiou Wang +6

Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, th…

cs.LG2024

HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices

Ao Zhou, Jianlei Yang, Yingjie Qi +5

Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Never…

cs.LG2024

GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration

Tong Qiao, Jianlei Yang, Yingjie Qi +5

Graph Neural Networks (GNNs) succeed significantly in many applications recently. However, balancing GNNs training runtime cost, memory consumption, and attainable accuracy for var…

cs.AR2024

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity

Cenlin Duan, Jianlei Yang, Yiou Wang +7

Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computatio…

cs.LG2024

Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems

Ao Zhou, Jianlei Yang, Tong Qiao +4

The key to device-edge co-inference paradigm is to partition models into computation-friendly and computation-intensive parts across the device and the edge, respectively. However,…

cs.LG2023★ 2 cited

TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices

Jianlei Yang, Jiacheng Liao, Fanding Lei +6

Developing deep learning models on tiny devices (e.g. Microcontroller units, MCUs) has attracted much attention in various embedded IoT applications. However, it is challenging to…

cs.AR2023

DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory

Cenlin Duan, Jianlei Yang, Xiaolin He +9

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been d…

cs.LG2023

Architectural Implications of GNN Aggregation Programming Abstractions

Yingjie Qi, Jianlei Yang, Ao Zhou +2

Graph neural networks (GNNs) have gained significant popularity due to the powerful capability to extract useful representations from graph data. As the need for efficient GNN comp…

cs.CV2023

Lossy and Lossless (L) Post-training Model Size Compression

Yumeng Shi, Shihao Bai, Xiuying Wei +2

Deep neural networks have delivered remarkable performance and have been widely used in various visual tasks. However, their huge size causes significant inconvenience for transmis…

cs.LG2023★ 1 cited

Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms

Ao Zhou, Jianlei Yang, Yingjie Qi +4

Graph neural networks (GNNs) have emerged as a popular strategy for handling non-Euclidean data due to their state-of-the-art performance. However, most of the current GNN model de…

cs.AR2022★ 20 cited

NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration

Yinglin Zhao, Jianlei Yang, Bing Li +7

The performance and efficiency of running large-scale datasets on traditional computing systems exhibit critical bottlenecks due to the existing "power wall" and "memory wall" prob…

cs.AR2022

Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform

Mingjun Li, Jianlei Yang, Yingjie Qi +6

Event cameras are bio-inspired vision sensors that asynchronously represent pixel-level brightness changes as event streams. Event-based monocular multi-view stereo (EMVS) is a tec…