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cs.ET2026
Cross-Layer Co-Design of Low-Latency Stateful Logic Adders with Printed Memristors
Fabian Seiler, Kerem Kagan Güclü, Hongrong Hu +3
Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean op…
cs.ET2026
An Instruction Set Architecture for IMPLY-based Memristive Processing-in-Array
Liam Splittgerber, Fabian Seiler, Nima TaheriNejad
The push towards expanded ultra-low-power edge computing necessitates hardware capable of operating under extremely strict energy constraints. Traditional Complementary Metal-Oxide…