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cs.AR2026

FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs

Jiawei Liang, Haotong Qin, Linfeng Du +7

Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable…

cs.AR2026

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs

Xiaofeng Zhou, Linfeng Du, Guangyu Hu +3

High-level synthesis (HLS) transforms an algorithmic description of hardware from a higher abstraction (e.g., C/C++) into a register-transfer level (RTL) design, offering reduced d…

cs.AR2026

FPPS: An FPGA-Based Point Cloud Processing System

Xiaofeng Zhou, Linfeng Du, Hanwei Fan +1

Point cloud processing is a computational bottleneck in autonomous driving systems, especially for real-time applications, while energy efficiency remains a critical system constra…

cs.AR2025

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration

Xingyu Liu, Jiawei Liang, Linfeng Du +5

In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task…

cs.AR2025

DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator

Xingyu Liu, Jiawei Liang, Yipu Zhang +5

We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand…

cs.AR2024

Fast and Practical Strassen's Matrix Multiplication using FPGAs

Afzal Ahmad, Linfeng Du, Wei Zhang

Matrix multiplication is a cornerstone operation in a wide array of scientific fields, including machine learning and computer graphics. The standard algorithm for matrix multiplic…