3 papers
cs.AR2023
GSA to HDL: Towards principled generation of dynamically scheduled circuits
Aditya Rajagopal, Diederik Adriaan Vink, Jianyi Cheng +1
High-level synthesis (HLS) refers to the automatic translation of a software program written in a high-level language into a hardware design. Modern HLS tools have moved away from…
cs.PL2023
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR
Jianyi Cheng, Samuel Coward, Lorenzo Chelini +2
High-level synthesis (HLS) is a process that automatically translates a software program in a high-level language into a low-level hardware description. However, the hardware desig…
cs.AR2023
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng +1
With the ever-growing popularity of Artificial Intelligence, there is an increasing demand for more performant and efficient underlying hardware. Convolutional Neural Networks (CNN…