2 papers
cs.AR2018
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
Steven Hoover, Ákos Hadnagy
Timing-abstract and transaction-level design using TL-Verilog have shown significant productivity gains for logic design. In this work, we explored the natural extension of transac…
cs.AR2018
Top-Down Transaction-Level Design with TL-Verilog
Steven Hoover, Ahmed Salman
Transaction-Level Verilog (TL-Verilog) is an emerging extension to SystemVerilog that supports a new design methodology, called transaction-level design. A transaction, in this met…