17 citations · 18 across the 6 of their papers we have counts for
6 papers
Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing
Yu-Wei Fan, Yuheng Yang, Christine Guo +4
Register-Transfer Level (RTL) simulation is widely used to test hardware before it is fabricated. To allow testing for security related information flow properties, such as confide…
Automatic ISA analysis for Secure Context Switching
Neelu S. Kalani, Thomas Bourgeat, Guerney D. H. Hunt +1
Instruction set architectures are complex, with hundreds of registers and instructions that can modify dozens of them during execution, variably on each instance. Prose-style ISA s…
RTL Verification for Secure Speculation Using Contract Shadow Logic
Qinhan Tan, Yuheng Yang, Thomas Bourgeat +2
Modern out-of-order processors face speculative execution attacks. Despite various proposed software and hardware mitigations to prevent such attacks, new attacks keep arising from…
Citadel: Simple Spectre-Safe Isolation For Real-World Programs That Share Memory
Jules Drean, Miguel Gomez-Garcia, Fisher Jepsen +2
Transient execution side-channel attacks, such as Spectre, have been shown to break almost all isolation primitives. We introduce a new security property we call relaxed microarchi…
Flexible Instruction-Set Semantics via Type Classes
Thomas Bourgeat, Ian Clester, Andres Erbsen +4
Instruction sets, from families like x86 and ARM, are at the center of many ambitious formal-methods projects. Many verification, synthesis, programming, and debugging tools rely o…
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Thomas Bourgeat, Ilia Lebedev, Andrew Wright +3
Recent attacks have broken process isolation by exploiting microarchitectural side channels that allow indirect access to shared microarchitectural state. Enclaves strengthen the p…