44 citations · 69 across the 6 of their papers we have counts for
6 papers · 1 filter
Democratizing Domain-Specific Computing
Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh +2
In the past few years, domain-specific accelerators (DSAs), such as Google's Tensor Processing Units, have shown to offer significant performance and energy efficiency over general…
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design
Licheng Guo, Yuze Chi, Jason Lau +9
In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, T…
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned
Jie Wang, Jason Cong
Systolic arrays have been widely used for accelerating HPC and deep learning applications. There is a plethora of previous works on the performance tuning of systolic arrays, but u…
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization
Young-kyu Choi, Yuze Chi, Jie Wang +2
With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applic…
Extending High-Level Synthesis for Task-Parallel Programs
Yuze Chi, Licheng Guo, Jason Lau +3
C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thank…
Rapid Cycle-Accurate Simulator for High-Level Synthesis
Yuze Chi, Young-kyu Choi, Jason Cong +1
A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA exp…