activity
20182024
most citedNicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM

19 citations · 39 across the 6 of their papers we have counts for

collaborators

6 papers

cs.CV2024★ 2 cited

Robust and Efficient Adversarial Defense in SNNs via Image Purification and Joint Detection

Weiran Chen, Qi Xu

Spiking Neural Networks (SNNs) aim to bridge the gap between neuroscience and machine learning by emulating the structure of the human nervous system. However, like convolutional n…

cs.AR2023★ 19 cited

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM

Junpeng Wang, Mengke Ge, Bo Ding +3

With the widespread use of deep neural networks(DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasi…

eess.SY2022

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs

Bo Ding, Jinglei Huang, Junpeng Wang +3

Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically re…

cs.AR2021

Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips

Mengke Ge, Xiaobing Ni, Qi Xu +4

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, w…

cs.AR2019★ 1 cited

Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips

Song Chen, Mengke Ge, Zhigang Li +3

The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generali…

cs.AR2018★ 17 cited

Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems

Song Chen, Jinglei Huang, Xiaodong Xu +1

Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfigura…