17 citations · 19 across the 5 of their papers we have counts for
5 papers
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs
Bo Ding, Jinglei Huang, Junpeng Wang +3
Modern field programmable gate array(FPGA) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. And FPGA-based partially dynamically re…
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips
Mengke Ge, Xiaobing Ni, Qi Xu +4
Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, w…
Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips
Song Chen, Mengke Ge, Zhigang Li +3
The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generali…
Adaptive 3D-IC TSV Fault Tolerance Structure Generation
Song Chen, Qi Xu, Bei Yu
In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of…
Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems
Song Chen, Jinglei Huang, Xiaodong Xu +1
Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfigura…