6 citations · 13 across the 11 of their papers we have counts for
11 papers
ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networks
Zachary Susskind, Aman Arora, Igor D. S. Miranda +9
The deployment of AI models on low-power, real-time edge devices requires accelerators for which energy, latency, and area are all first-order concerns. There are many approaches t…
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
Zhigang Wei, Aman Arora, Ruihao Li +1
Machine Learning (ML) has been widely adopted in design exploration using high level synthesis (HLS) to give a better and faster performance, and resource and power estimation at v…
CoMeFa: Compute-in-Memory Blocks for FPGAs
Aman Arora, Tanmay Anand, Aatman Borda +4
Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal Proces…
Weightless Neural Networks for Efficient Edge Inference
Zachary Susskind, Aman Arora, Igor Dantas Dos Santos Miranda +8
Weightless Neural Networks (WNNs) are a class of machine learning model which use table lookups to perform inference. This is in contrast with Deep Neural Networks (DNNs), which us…
Neuro-Symbolic AI: An Emerging Class of AI Workloads and their Characterization
Zachary Susskind, Bryce Arden, Lizy K. John +2
Neuro-symbolic artificial intelligence is a novel area of AI research which seeks to combine traditional rules-based AI approaches with modern deep learning techniques. Neuro-symbo…
Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs
Aman Arora, Bagus Hanindhito, Lizy K. John
The configurable building blocks of current FPGAs -- Logic blocks (LBs), Digital Signal Processing (DSP) slices, and Block RAMs (BRAMs) -- make them efficient hardware accelerators…
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Aman Arora, Andrew Boutros, Daniel Rauch +9
With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better quality-of-re…
Virtual-Link: A Scalable Multi-Producer, Multi-Consumer Message Queue Architecture for Cross-Core Communication
Qinzhe Wu, Jonathan Beard, Ashen Ekanayake +2
Cross-core communication is increasingly a bottleneck as the number of processing elements increase per system-on-chip. Typical hardware solutions to cross-core communication are o…
Demystifying the MLPerf Benchmark Suite
Snehil Verma, Qinzhe Wu, Bagus Hanindhito +4
MLPerf, an emerging machine learning benchmark suite strives to cover a broad range of applications of machine learning. We present a study on its characteristics and how the MLPer…
Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction
Shuang Song, Xu Liu, Qinzhe Wu +3
Graph processing systems are important in the big data domain. However, processing graphs in parallel often introduces redundant computations in existing algorithms and models. Pri…
BigDataBench-MT: A Benchmark Tool for Generating Realistic Mixed Data Center Workloads
Rui Han, Shulin Zhan, Chenrong Shao +5
Long-running service workloads (e.g. web search engine) and short-term data analysis workloads (e.g. Hadoop MapReduce jobs) co-locate in today's data centers. Developing realistic…