13 citations · 22 across the 6 of their papers we have counts for
5 papers · 1 filter
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are…
Constructing a Weak Memory Model
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright +2
Weak memory models are a consequence of the desire on part of architects to preserve all the uniprocessor optimizations while building a shared memory multiprocessor. The efforts t…
Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications
Mehdi Alipour, Mostafa E. Salehi, Hesamodin shojaei baghini
In the future, embedded processors must process more computation-intensive network applications and internet traffic and packet-processing tasks become heavier and sophisticated. S…
Performance-Optimum Superscalar Architecture for Embedded Applications
Mehdi Alipour, Mostafa E. Salehi
Embedded applications are widely used in portable devices such as wireless phones, personal digital assistants, laptops, etc. High throughput and real time requirements are especia…
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
Mehdi Alipour, Hojjat Taghdisi
According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive…