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20192026
most citedAn Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

90 citations · 229 across the 24 of their papers we have counts for

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Showing cs.ARShow all

16 papers · 1 filter

cs.AR2026

ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents

Stef Cuyckens, Mihaela Jivanescu, Jun Yin +2

Large language model (LLM) agents optimize the power, performance, and area (PPA) of register-transfer-level (RTL) designs by iterating over edits, synthesis, and PPA analysis, pay…

cs.AR2026

HiKV: Hierarchical Importance-Aware KV Cache with Hardware Acceleration for LLM Decoding

Chao Fang, Jun Yin, Man Shi +1

With the rapid adoption of long-context large language models (LLMs), the continuously growing KV cache during decoding has become the critical memory bottleneck. To tackle this ch…

cs.AR2026

CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-Device

Ye Lin, Chao Fang, Xiaoyong Song +4

Edge deployment of low-batch large language models (LLMs) faces critical memory bandwidth bottlenecks when executing memory-intensive general matrix-vector multiplications (GEMV) o…

cs.AR2025★ 1 cited

Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration

Stef Cuyckens, Xiaoling Yi, Robin Geens +4

Emerging continual learning applications necessitate next-generation neural processing unit (NPU) platforms to support both training and inference operations. The promising Microsc…

cs.AR2025

P3-LLM: An Integrated NPU-PIM Accelerator for Edge LLM Inference Using Hybrid Numerical Formats

Yuzong Chen, Chao Fang, Xilai Dai +4

The substantial memory bandwidth and computational demands of large language models (LLMs) present critical challenges for efficient inference. To tackle this, the literature has e…

cs.AR2025★ 1 cited

iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator

Stef Cuyckens, Ryan Antonio, Chao Fang +1

Implantable devices for reliable intracranial electroencephalography (iEEG) require efficient, accurate, and real-time detection of seizures. Dense hyperdimensional computing (HDC)…

cs.AR2025★ 1 cited

SnipSnap: A Joint Compression Format and Dataflow Co-Optimization Framework for Efficient Sparse LLM Accelerator Design

Junyi Wu, Chao Fang, Zhongfeng Wang

The growing scale of large language models (LLMs) has intensified demands on computation and memory, making efficient inference a key challenge. While sparsity can reduce these cos…

cs.AR2025

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

Qiong Li, Chao Fang, Longwei Huang +2

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for ligh…

cs.AR2025★ 4 cited

Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning

Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy +2

Autonomous robots require efficient on-device learning to adapt to new environments without cloud dependency. For this edge training, Microscaling (MX) data types offer a promising…

cs.AR2024★ 15 cited

Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format

Chao Fang, Man Shi, Robin Geens +3

The widely-used, weight-only quantized large language models (LLMs), which leverage low-bit integer (INT) weights and retain floating-point (FP) activations, reduce storage require…

cs.AR2024★ 11 cited

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference

Chuanning Wang, Chao Fang, Xiao Wu +2

Deploying deep neural networks (DNNs) on those resource-constrained edge platforms is hindered by their substantial computation and storage demands. Quantized multi-precision DNNs,…

cs.AR2024★ 14 cited

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference

Chuanning Wang, Chao Fang, Xiao Wu +2

RISC-V processors encounter substantial challenges in deploying multi-precision deep neural networks (DNNs) due to their restricted precision support, constrained throughput, and s…

cs.AR2024★ 9 cited

BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge

Yuhao Ji, Chao Fang, Zhongfeng Wang

Existing binary Transformers are promising in edge deployment due to their compact model size, low computational complexity, and considerable inference accuracy. However, deploying…

cs.AR2023★ 16 cited

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge

Longwei Huang, Chao Fang, Qiong Li +2

Extreme edge platforms, such as in-vehicle smart devices, require efficient deployment of quantized deep neural networks (DNNs) to enable intelligent applications with limited amou…

cs.AR2023★ 10 cited

PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

Qiong Li, Chao Fang, Zhongfeng Wang

Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However,…

cs.AR2022★ 90 cited

An Algorithm-Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

Chao Fang, Aojun Zhou, Zhongfeng Wang

The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers due to immense param…