activity
20192025
most citedLow-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays

14 citations · 24 across the 7 of their papers we have counts for

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5 papers · 1 filter

cs.AR2025★ 4 cited

DSLR-CNN: Efficient CNN Acceleration using Digit-Serial Left-to-Right Arithmetic

Malik Zohaib Nisar, Muhammad Sohail Ibrahim, Saeid Gorgin +2

Digit-serial arithmetic has emerged as a viable approach for designing hardware accelerators, reducing interconnections, area utilization, and power consumption. However, conventio…

cs.AR2024

L2R-CIPU: Efficient CNN Computation with Left-to-Right Composite Inner Product Units

Malik Zohaib Nisar, Mohammad Sohail Ibrahim, Muhammad Usman +1

This paper proposes a composite inner-product computation unit based on left-to-right (LR) arithmetic for the acceleration of convolution neural networks (CNN) on hardware. The eff…

cs.AR2023

DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator

Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar +1

We propose a Digit-Serial Left-tO-righT (DSLOT) arithmetic based processing technique called DSLOT-NN with aim to accelerate inference of the convolution operation in the deep neur…

cs.AR2023★ 14 cited

Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays

Muhammad Usman, Milos Ercegovac, Jeong-A Lee

Multiplication is indispensable and is one of the core operations in many modern applications including signal processing and neural networks. Conventional right-to-left (RL) multi…

cs.AR2022★ 6 cited

Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays

Muhammad Usman, Jeong-A Lee, Milos D. Ercegovac

We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<…