5 citations · 21 across the 15 of their papers we have counts for
16 papers
System-Level Performance Modeling of Photonic In-Memory Computing
Jebacyril Arockiaraj, Sasindu Wijeratne, Sugeet Sunder +4
Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwid…
AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Matricized Tensor Times Khatri-Rao Product (MTTKRP) is the computational bottleneck in sparse tensor decomposition. As real-world sparse tensors grow to billions of nonzeros, they…
Predictive Performance of Photonic SRAM-based In-Memory Computing for Tensor Decomposition
Sasindu Wijeratne, Sugeet Sunder, Md Abdullah-Al Kaiser +4
Photonics-based in-memory computing systems have demonstrated a significant speedup over traditional transistor-based systems because of their ultra-fast operating frequencies and…
Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Sparse Matricized Tensor Times Khatri-Rao Product (spMTTKRP) is the bottleneck kernel of sparse tensor decomposition. In tensor decomposition, spMTTKRP is performed iteratively alo…
Sparse MTTKRP Acceleration for Tensor Decomposition on GPU
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Sparse Matricized Tensor Times Khatri-Rao Product (spMTTKRP) is the bottleneck kernel of sparse tensor decomposition. In this work, we propose a GPU-based algorithm design to addre…
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images
Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan +2
Synthetic Aperture Radar (SAR) images are commonly utilized in military applications for automatic target recognition (ATR). Machine learning (ML) methods, such as Convolutional Ne…
Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Sparse Matricized Tensor Times Khatri-Rao Product (spMTTKRP) is the most time-consuming compute kernel in sparse tensor decomposition. In this paper, we introduce a novel algorithm…
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
Paul Chen, Pavan Manjunath, Sasindu Wijeratne +2
Graph Neural Networks (GNNs) have revolutionized many Machine Learning (ML) applications, such as social network analysis, bioinformatics, etc. GNN inference can be accelerated by…
Graph Neural Network for Accurate and Low-complexity SAR ATR
Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan +2
Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR) is the key technique for remote sensing image recognition. The state-of-the-art works exploit the deep convolution…
Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA
Sasindu Wijeratne, Akhilesh Jaiswal, Ajey P. Jacob +2
Electrical static random memory (E-SRAM) is the current standard for internal static memory in Field Programmable Gate Array (FPGA). Despite the dramatic improvement in E-SRAM tech…
Towards Programmable Memory Controller for Tensor Decomposition
Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan +1
Tensor decomposition has become an essential tool in many data science applications. Sparse Matricized Tensor Times Khatri-Rao Product (MTTKRP) is the pivotal kernel in tensor deco…
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna
Tensor decomposition has become an essential tool in many applications in various domains, including machine learning. Sparse Matricized Tensor Times Khatri-Rao Product (MTTKRP) is…
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya +1
Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. There…
Programmable FPGA-based Memory Controller
Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen +2
Even with generational improvements in DRAM technology, memory access latency still remains the major bottleneck for application accelerators, primarily due to limitations in memor…
A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
Ruizhi Zhang, Sasindu Wijeratne, Yang Yang +2
Hash table is a fundamental data structure for quick search and retrieval of data. It is a key component in complex graph analytics and AI/ML applications. State-of-the-art paralle…
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera +2
Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in-network service deployment, there is a huge d…