1 citations · 1 across the 2 of their papers we have counts for
2 papers
cs.OS2020
Leveraging Architectural Support of Three Page Sizes with Trident
Venkat Sri Sai Ram, Ashish Panwar, Arkaprava Basu
Large pages are commonly deployed to reduce address translation overheads for big-memory workloads. Modern x86-64 processors from Intel and AMD support two large page sizes -- 1GB…
cs.OS2019★ 1 cited
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
Reto Achermann, Ashish Panwar, Abhishek Bhattacharjee +2
Multi-socket machines with 1-100 TBs of physical memory are becoming prevalent. Applications running on multi-socket machines suffer non-uniform bandwidth and latency when accessin…