2 papers
cs.CR2019
DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs
Jacob T. Grycel, Robert J. Walls
Advanced Encryption Standard (AES) implementations on Field Programmable Gate Arrays (FPGA) commonly focus on maximizing throughput at the cost of utilizing high volumes of FPGA sl…
cs.CR2019
ERHARD-RNG: A Random Number Generator Built from Repurposed Hardware in Embedded Systems
Jacob Grycel, Robert J. Walls
Quality randomness is fundamental to cryptographic operations but on embedded systems good sources are (seemingly) hard to find. Rather than use expensive custom hardware, our ERHA…