2 papers
eess.SP2019
A 130-MS/s 10-Bit Asynchronous SAR ADC with 55.2 dB SNDR
Ayan Mandal, Asish Koruprolu
This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consi…
cs.CC2011
Boolean Satisfiability using Noise Based Logic
Pey-Chang Kent Lin, Ayan Mandal, Sunil P Khatri
In this paper, we present a novel algorithm to solve the Boolean Satisfiability (SAT) problem, using noise-based logic (NBL). Contrary to what the name may suggest, NBL is not a ra…