7 citations · 24 across the 12 of their papers we have counts for
Showing 2007Show all
2 papers · 1 filter
cs.AR2007
Statistical Timing Based Optimization using Gate Sizing
Aseem Agarwal, Kaviraj Chopra, David Blaauw
The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimiza…
cs.AR2007
DVS for On-Chip Bus Designs Based on Timing Error Correction
Himanshu Kaul, Dennis Sylvester, David Blaauw +2
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern…