4 citations · 6 across the 6 of their papers we have counts for
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cs.AR2021★ 4 cited
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Sung Kim, Morteza Fayazi, Alhad Daftardar +10
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristi…
cs.AR2018
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
Charles Eckert, Xiaowei Wang, Jingcheng Wang +5
This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep…