7 citations · 24 across the 12 of their papers we have counts for
4 papers · 1 filter
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm
Sung Kim, Morteza Fayazi, Alhad Daftardar +10
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristi…
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
Charles Eckert, Xiaowei Wang, Jingcheng Wang +5
This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep…
Statistical Timing Based Optimization using Gate Sizing
Aseem Agarwal, Kaviraj Chopra, David Blaauw
The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimiza…
DVS for On-Chip Bus Designs Based on Timing Error Correction
Himanshu Kaul, Dennis Sylvester, David Blaauw +2
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern…