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cs.AR2024
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
Andreas Böttcher, Martin Kumm
The major challenge when designing multipliers for FPGAs is to address several trade-offs: On the one hand at the performance level and on the other hand at the resource level util…
cs.AR2024★ 1 cited
Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
Andreas Böttcher, Martin Kumm
There is a recent trend in artificial intelligence (AI) inference towards lower precision data formats down to 8 bits and less. As multiplication is the most complex operation in t…