222 citations · 243 across the 10 of their papers we have counts for
10 papers
PEak: A Single Source of Truth for Hardware Design and Verification
Caleb Donovick, Ross Daly, Jackson Melchert +4
Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification lang…
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays
Taeyoung Kong, Kalhan Koul, Priyanka Raina +2
Domain-specific accelerators are used in various computing systems ranging from edge devices to data centers. Coarse-grained reconfigurable arrays (CGRAs) represent an architectura…
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
Jackson Melchert, Keyi Zhang, Yuchen Mei +3
The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power,…
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Jackson Melchert, Yuchen Mei, Kalhan Koul +3
While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, pipelining applications running on CGRAs is required to ensure…
Enabling Reusable Physical Design Flows with Modular Flow Generators
Alex Carsello, James Thomas, Ankita Nayak +4
Achieving high code reuse in physical design flows is challenging but increasingly necessary to build complex systems. Unfortunately, existing approaches based on parameterized Tcl…
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory
Weier Wan, Rajkumar Kubendran, Clemens Schaefer +11
Realizing today's cloud-level artificial intelligence functionalities directly on devices distributed at the edge of the internet calls for edge hardware capable of processing mult…
Compiling Halide Programs to Push-Memory Accelerators
Qiaoyi Liu, Dillon Huff, Jeff Setter +8
Image processing and machine learning applications benefit tremendously from hardware acceleration, but existing compilers target either FPGAs, which sacrifice power and performanc…
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis
Jackson Melchert, Kathleen Feng, Caleb Donovick +5
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running…
Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks
Makena Low, Priyanka Raina
For several skin conditions such as vitiligo, accurate segmentation of lesions from skin images is the primary measure of disease progression and severity. Existing methods for vit…
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
Xuan Yang, Mingyu Gao, Qiaoyi Liu +9
We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops o…