9 citations · 9 across the 6 of their papers we have counts for
6 papers
A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms
Tom Glint, Chandan Kumar Jha, Manu Awasthi +1
Traditional computers with von Neumann architecture are unable to meet the latency and scalability challenges of Deep Neural Network (DNN) workloads. Various DNN accelerators based…
Learning by Cheating : An End-to-End Zero Shot Framework for Autonomous Drone Navigation
Praveen Venkatesh, Viraj Shah, Vrutik Shah +2
This paper proposes a novel framework for autonomous drone navigation through a cluttered environment. Control policies are learnt in a low-level environment during training and ar…
HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy
Sarabjeet Singh, Neelam Surana, Pranjali Jain +2
In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack…
Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications
Chandan Kumar Jha, Shreyas Singh, Riddhi Thakker +2
In this paper, we propose Zero Aware Configurable Data Encoding by Skipping Transfer (ZAC-DEST), a data encoding scheme to reduce the energy consumption of DRAM channels, specifica…
Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications
Varun Gohil, Sumit Walia, Joycee Mekie +1
Today, almost all computer systems use IEEE-754 floating point to represent real numbers. Recently, posit was proposed as an alternative to IEEE-754 floating point as it has better…
SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol
Sai Aparna Aketi, Smriti Gupta, Huimei Cheng +2
The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are…