112 citations · 172 across the 13 of their papers we have counts for
6 papers · 1 filter
Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators
Wooseok Choi, Tommaso Stecconi, Donato Francesco Falcone +14
Resistive memory (ReRAM) technologies with crossbar array architectures hold significant potential for analog AI accelerator hardware, enabling both in-memory inference and trainin…
Study of Resistive Switching Dynamics and Memory States Equilibria in Analog Filamentary Conductive-Metal-Oxide/HfOx ReRAM via Compact Modeling
Matteo Galetta, Donato Francesco Falcone, Victoria Clerico +7
Resistive Random Access Memory (ReRAM) devices offer a promising solution for next-generation non-volatile memory and neuromorphic computing systems. Yet, existing compact models f…
Analytical Modelling of the Transport in Analog Filamentary Conductive-Metal-Oxide/HfOx ReRAM Devices
Donato Francesco Falcone, Stephan Menzel, Tommaso Stecconi +4
The recent co-optimization of memristive technologies and programming algorithms enabled neural networks training with in-memory computing systems. In this context, novel analog fi…
Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks
Wooseok Choi, Thomas van Bodegraven, Jelle Verest +8
We demonstrate the first hardware implementation of an oscillatory neural network (ONN) utilizing resistive memory (ReRAM) for coupling elements. A ReRAM crossbar array chip, integ…
All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices
Donato Francesco Falcone, Victoria Clerico, Wooseok Choi +9
Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or trainin…
A back-end, CMOS compatible ferroelectric Field Effect Transistor for synaptic weights
Mattia Halter, Laura Bégon-Lours, Valeria Bragaglia +5
Neuromorphic computing architectures enable the dense co-location of memory and processing elements within a single circuit. This co-location removes the communication bottleneck o…