161 citations · 217 across the 9 of their papers we have counts for
6 papers · 1 filter
Scale-out Systolic Arrays
Ahmet Caner Yüzügüler, Canberk Sönmez, Mario Drumond +3
Multi-pod systolic arrays are emerging as the architecture of choice in DNN inference accelerators. Despite their potential, designing multi-pod systolic arrays to maximize effecti…
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Mohammad Sadrosadati, Amirhossein Mirhosseini, Ali Hajiabadi +7
Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bot…
SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators
Javier Picorel, Seyed Alireza Sanaee Kohroudi, Zi Yan +3
Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the are…
Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms
Phillip Stanley-Marbell, Armin Alaghi, Michael Carbin +13
When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, programming languages, and sys…
Design Guidelines for High-Performance SCM Hierarchies
Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel +4
With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few…
Near-Memory Address Translation
Javier Picorel, Djordje Jevdjic, Babak Falsafi
Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed i…