3 papers
cs.AR2025
4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation
Fuyuki Kihara, Seiji Uenohara, Satoshi Awamura +3
Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. Howeve…
cs.AR2025
CuLD: Current-Limiting Differential Reading Circuit for Current-Based Compute-in-Memory
Seiji Uenohara, Satoshi Awamura, Norio Hattori
This paper proposes a circuit configuration that addresses the issue of deviation in the multiply-accumulate (MAC) results when numerous word lines are simultaneously opened in cur…
eess.SP2020
Time-domain digital-to-analog converter for spiking neural network hardware
Seiji Uenohara, Kazuyuki Aihara
We propose a new digital-to-analog converter (DAC) for realizing a synapse circuit of mixed-signal spiking neural networks. We named this circuit "time-domain DAC (TDAC)". This pro…