26 citations · 95 across the 22 of their papers we have counts for
22 papers
NVCiM-PT: An NVCiM-assisted Prompt Tuning Framework for Edge LLMs
Ruiyang Qin, Pengyu Ren, Zheyu Yan +7
Large Language Models (LLMs) deployed on edge devices, known as edge LLMs, need to continuously fine-tune their model parameters from user-generated data under limited resource con…
Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on the Edge
Ruiyang Qin, Dancheng Liu, Gelei Xu +7
The combination of Large Language Models (LLM) and Automatic Speech Recognition (ASR), when deployed on edge devices (called edge ASR-LLM), can serve as a powerful personalized ass…
A 10.60 W 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
Yifan Qin, Zhenge Jia, Zheyu Yan +9
This paper proposes an ultra-low power, mixed-bit-width sparse convolutional neural network (CNN) accelerator to accelerate ventricular arrhythmia (VA) detection. The chip achieves…
Rethinking Medical Anomaly Detection in Brain MRI: An Image Quality Assessment Perspective
Zixuan Pan, Jun Xia, Zheyu Yan +7
Reconstruction-based methods, particularly those leveraging autoencoders, have been widely adopted for anomaly detection task in brain MRI. Unlike most existing works try to improv…
TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators
Yifan Qin, Zheyu Yan, Zixuan Pan +3
Compute-in-memory (CIM) accelerators using non-volatile memory (NVM) devices offer promising solutions for energy-efficient and low-latency Deep Neural Network (DNN) inference exec…
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices
Ruiyang Qin, Dancheng Liu, Chenhui Xu +9
The scaling laws have become the de facto guidelines for designing large language models (LLMs), but they were studied under the assumption of unlimited computing resources for bot…
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures
Ruiyang Qin, Zheyu Yan, Dewen Zeng +8
Large Language Models (LLMs) deployed on edge devices learn through fine-tuning and updating a certain portion of their parameters. Although such learning methods can be optimized…
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models
Ruiyang Qin, Yuting Hu, Zheyu Yan +3
Neural Architecture Search (NAS) has become the de fecto tools in the industry in automating the design of deep neural networks for various applications, especially those driven by…
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi
Architectures that incorporate Computing-in-Memory (CiM) using emerging non-volatile memory (NVM) devices have become strong contenders for deep neural network (DNN) acceleration d…
Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi
Emerging non-volatile memory (NVM)-based Computing-in-Memory (CiM) architectures show substantial promise in accelerating deep neural networks (DNNs) due to their exceptional energ…
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise
Zheyu Yan, Yifan Qin, Wujie Wen +2
Compute-in-Memory (CiM), built upon non-volatile memory (NVM) devices, is promising for accelerating deep neural networks (DNNs) owing to its in-situ data processing capability and…
On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators
Zheyu Yan, Yifan Qin, Xiaobo Sharon Hu +1
Deep Neural Networks (DNNs) have demonstrated impressive performance across a wide range of tasks. However, deploying DNNs on edge devices poses significant challenges due to strin…
NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Accelerators
Yifan Qin, Zheyu Yan, Dailin Gan +5
Compute-in-memory accelerators built upon non-volatile memory devices excel in energy efficiency and latency when performing deep neural network (DNN) inference, thanks to their in…
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi
Computing-in-Memory (CiM) architectures based on emerging non-volatile memory (NVM) devices have demonstrated great potential for deep neural network (DNN) acceleration thanks to t…
On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi
Computing-in-memory with emerging non-volatile memory (nvCiM) is shown to be a promising candidate for accelerating deep neural networks (DNNs) with high energy efficiency. However…
A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators
Bingqian Lu, Zheyu Yan, Yiyu Shi +1
In view of the performance limitations of fully-decoupled designs for neural architectures and accelerators, hardware-software co-design has been emerging to fully reap the benefit…
SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators
Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi
Computing-in-Memory architectures based on non-volatile emerging memories have demonstrated great potential for deep neural network (DNN) acceleration thanks to their high energy e…
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu +1
Differentiable neural architecture search (DNAS) is known for its capacity in the automatic generation of superior neural networks. However, DNAS based methods suffer from memory u…
Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search
Zheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu +1
Emerging device-based Computing-in-memory (CiM) has been proved to be a promising candidate for high-energy efficiency deep neural network (DNN) computations. However, most emergin…
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Lei Yang, Zheyu Yan, Meng Li +6
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs).…
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Weiwen Jiang, Qiuwen Lou, Zheyu Yan +4
Co-exploration of neural architectures and hardware design is promising to simultaneously optimize network accuracy and hardware efficiency. However, state-of-the-art neural archit…
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
Zheyu Yan, Yiyu Shi, Wang Liao +3
Deep Neural Network has proved its potential in various perception tasks and hence become an appealing option for interpretation and data processing in security sensitive systems.…