activity
20182020
most citedAN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs

60 citations · 89 across the 3 of their papers we have counts for

collaborators

5 papers

cs.DC202014 cited

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka

In this paper we evaluate the performance of FPGAs for high-order stencil computation using High-Level Synthesis. We show that despite the higher computation intensity and on-chip…

cs.DC202060 cited

AN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs

Kazuaki Matsumura, Hamid Reza Zohouri, Mohamed Wahib +2

Stencil computation is one of the most widely-used compute patterns in high performance computing applications. Spatial and temporal blocking have been proposed to overcome the mem…

cs.AR201915 cited

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Hamid Reza Zohouri, Satoshi Matsuoka

Supported by their high power efficiency and recent advancements in High Level Synthesis (HLS), FPGAs are quickly finding their way into HPC and cloud systems. Large amounts of wor…

cs.DC2018

High Performance Computing with FPGAs and OpenCL

Hamid Reza Zohouri

In this work we evaluate the potential of FPGAs for accelerating HPC workloads as a more power-efficient alternative to GPUs. Using High-Level Synthesis and a large set of optimiza…

cs.DC2018

Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL

Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka

Recent developments in High Level Synthesis tools have attracted software programmers to accelerate their high-performance computing applications on FPGAs. Even though it has been…