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20202026
most citedArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining

19 citations · 73 across the 28 of their papers we have counts for

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Showing 2025Show all

10 papers · 1 filter

cs.AR2025

H-FA: A Hybrid Floating-Point and Logarithmic Approach to Hardware Accelerated FlashAttention

Kosmas Alexandridis, Giorgos Dimitrakopoulos

Transformers have significantly advanced AI and machine learning through their powerful attention mechanism. However, computing attention on long sequences can become a computation…

cs.LG2025

Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors

Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos

Attention is a core operation in numerous machine learning and artificial intelligence models. This work focuses on the acceleration of attention kernel using FlashAttention algori…

cs.LG2025

Custom Algorithm-based Fault Tolerance for Attention Layers in Transformers

Vasileios Titopoulos, Kosmas Alexandridis, Giorgos Dimitrakopoulos

Transformers and large language models (LLMs), powered by the attention mechanism, have transformed numerous AI applications, driving the need for specialized hardware accelerators…

cs.AR2025

High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic

George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos

The Number Theoretic Transform (NTT) is a fundamental operation in privacy-preserving technologies, particularly within fully homomorphic encryption (FHE). The efficiency of NTT co…

cs.AR2025

Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators

Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos

Attention mechanisms, particularly within Transformer architectures and large language models (LLMs), have revolutionized sequence modeling in machine learning and artificial intel…

cs.AR2025

Efficient Implementation of RISC-V Vector Permutation Instructions

Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos +1

RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions t…

cs.LG2025

FLASH-D: FlashAttention with Hidden Softmax Division

Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos

The transformer's attention mechanism has revolutionized AI and machine learning, with its efficient computation being crucial to its performance. However, calculating attention in…

cs.AR2025

Periodic Online Testing for Sparse Systolic Tensor Arrays

Christodoulos Peltekis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Modern Machine Learning (ML) applications often benefit from structured sparsity, a technique that efficiently reduces model complexity and simplifies handling of sparse data in ha…

cs.AR2025

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs

Vasileios Titopoulos, George Alexakis, Kosmas Alexandridis +2

The deployment of Machine Learning (ML) applications at the edge on resource-constrained devices has accentuated the need for efficient ML processing on low-cost processors. While…

cs.AR2025

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors

Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis +2

Structured sparsity has been proposed as an efficient way to prune the complexity of Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. Acc…