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20202026
most citedDeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity

4 citations · 5 across the 23 of their papers we have counts for

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19 papers · 1 filter

cs.AR2026

High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture

George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos

Post-quantum cryptography and privacy-preserving technologies are expected to play a central role in future secure communication systems. Lattice-based PQC schemes such as ML-KEM (…

cs.AR2026

MIVE: A Minimalist Integer Vector Engine for Softmax LayerNorm and RMSNorm Acceleration

Kosmas Alexandridis, Giorgos Dimitrakopoulos

The rapid growth of Large Language Models (LLMs) has intensified the need for specialized hardware accelerators that can satisfy stringent inference latency and power constraints.…

cs.AR2025

H-FA: A Hybrid Floating-Point and Logarithmic Approach to Hardware Accelerated FlashAttention

Kosmas Alexandridis, Giorgos Dimitrakopoulos

Transformers have significantly advanced AI and machine learning through their powerful attention mechanism. However, computing attention on long sequences can become a computation…

cs.AR2025

High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic

George Alexakis, Dimitrios Schoinianakis, Giorgos Dimitrakopoulos

The Number Theoretic Transform (NTT) is a fundamental operation in privacy-preserving technologies, particularly within fully homomorphic encryption (FHE). The efficiency of NTT co…

cs.AR2025

Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators

Kosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos

Attention mechanisms, particularly within Transformer architectures and large language models (LLMs), have revolutionized sequence modeling in machine learning and artificial intel…

cs.AR2025

Efficient Implementation of RISC-V Vector Permutation Instructions

Vasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos +1

RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions t…