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20192021
most citedComposing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

15 citations · 66 across the 8 of their papers we have counts for

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6 papers · 1 filter

cs.AR2021★ 1 cited

Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models

Dan Alexandrescu, Aneesh Balakrishnan, Thomas Lange +1

Typical design flows are hierarchical and rely on assembling many individual technology elements from standard cells to complete boards. Providers use compact models to provide sim…

cs.AR2021★ 15 cited

Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2

Rapidly shrinking technology node and voltage scaling increase the susceptibility of Soft Errors in digital circuits. Soft Errors are radiation-induced effects while the radiation…

cs.AR2021★ 8 cited

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2

As an alternative to traditional fault injection-based methodologies and to explore the applicability of modern machine learning algorithms in the field of reliability engineering,…

cs.AR2021★ 11 cited

Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors

Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2

The paper is proposing a methodology for modeling a gate-level netlist using a Graph Convolutional Network (GCN). The model predicts the overall functional de-rating factors of seq…

cs.AR2020

Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features

Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux +2

Selective mitigation or selective hardening is an effective technique to obtain a good trade-off between the improvements in the overall reliability of a circuit and the hardware o…

cs.AR2020★ 3 cited

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks

Thomas Lange, Maximilien Glorieux, Dan Alexandrescu +1

With technology scaling, lower supply voltages, and higher operating frequencies clock distribution networks become more and more vulnerable to transients faults. These faults can…