activity
20202024
most citedAccelerator-aware Neural Network Design using AutoML

49 citations · 178 across the 10 of their papers we have counts for

collaborators

10 papers

cs.CV2024★ 22 cited

MobileNetV4 -- Universal Models for the Mobile Ecosystem

Danfeng Qin, Chas Leichner, Manolis Delakis +11

We present the latest generation of MobileNets, known as MobileNetV4 (MNv4), featuring universally efficient architecture designs for mobile devices. At its core, we introduce the…

cs.DC2022

Searching for Efficient Neural Architectures for On-Device ML on Edge TPUs

Berkin Akin, Suyog Gupta, Yun Long +6

On-device ML accelerators are becoming a standard in modern mobile system-on-chips (SoC). Neural architecture search (NAS) comes to the rescue for efficiently utilizing the high co…

cs.AR2021★ 2 cited

Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks

Amirali Boroumand, Saugata Ghose, Berkin Akin +5

Emerging edge computing platforms often contain machine learning (ML) accelerators that can accelerate inference for a wide range of neural network (NN) models. These models are de…

cs.AR2021★ 20 cited

Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models

Amirali Boroumand, Saugata Ghose, Berkin Akin +5

As the need for edge computing grows, many modern consumer devices now contain edge machine learning (ML) accelerators that can compute a wide range of neural network (NN) models w…

cs.LG2021★ 17 cited

Rethinking Co-design of Neural Architectures and Hardware Accelerators

Yanqi Zhou, Xuanyi Dong, Berkin Akin +7

Neural architectures and hardware accelerators have been two driving forces for the progress in deep learning. Previous works typically attempt to optimize hardware given a fixed m…

cs.LG2021★ 13 cited

Apollo: Transferable Architecture Exploration

Amir Yazdanbakhsh, Christof Angermueller, Berkin Akin +7

The looming end of Moore's Law and ascending use of deep learning drives the design of custom accelerators that are optimized for specific neural architectures. Architecture explor…

cs.LG2021★ 10 cited

An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks

Kiran Seshadri, Berkin Akin, James Laudon +2

Edge TPUs are a domain of accelerators for low-power, edge devices and are widely used in various Google products such as Coral and Pixel devices. In this paper, we first discuss t…

cs.CV2020★ 4 cited

Discovering Multi-Hardware Mobile Models via Architecture Search

Grace Chu, Okan Arikan, Gabriel Bender +7

Hardware-aware neural architecture designs have been predominantly focusing on optimizing model performance on single hardware and model development complexity, where another impor…

cs.CV2020★ 41 cited

MobileDets: Searching for Object Detection Architectures for Mobile Accelerators

Yunyang Xiong, Hanxiao Liu, Suyog Gupta +7

Inverted bottleneck layers, which are built upon depthwise convolutions, have been the predominant building blocks in state-of-the-art object detection models on mobile devices. In…

eess.SP2020★ 49 cited

Accelerator-aware Neural Network Design using AutoML

Suyog Gupta, Berkin Akin

While neural network hardware accelerators provide a substantial amount of raw compute throughput, the models deployed on them must be co-designed for the underlying hardware archi…