8 citations · 8 across the 3 of their papers we have counts for
3 papers
cs.AR2025
NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities
James Read, Ming-Yen Lee, Wei-Hsing Huang +3
The exponential growth of artificial intelligence (AI) applications has exposed the inefficiency of conventional von Neumann architectures, where frequent data transfers between co…
cs.ET2025
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories
Faaiq Waqar, Jiahao Zhang, Anni Lu +3
This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, sign…
cs.ET2020★ 8 cited
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training
Xiaochen Peng, Shanshi Huang, Hongwu Jiang +2
DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from device-level, to circuit-l…