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cs.LG2025
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie +3
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulatio…
cs.LG2021★ 1 cited
CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction
Dingcheng Yang, Wenjian Yu, Yuanbo Guo +1
Accurate capacitance extraction is becoming more important for designing integrated circuits under advanced process technology. The pattern matching based full-chip extraction meth…
cs.LG2020
DP-Net: Dynamic Programming Guided Deep Neural Network Compression
Dingcheng Yang, Wenjian Yu, Ao Zhou +3
In this work, we propose an effective scheme (called DP-Net) for compressing the deep neural networks (DNNs). It includes a novel dynamic programming (DP) based algorithm to obtain…