23 citations · 35 across the 4 of their papers we have counts for
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RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions
Takuto Kanamori, Hiromu Miyazaki, Kenji Kise
In this paper, we propose a high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions targeting on FPGA. The compressed instruction…
RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors
Md Ashraful Islam, Hiromu Miyazaki, Kenji Kise
RISC-V, an open instruction set architecture, is getting the attention of soft processor developers. Implementing only a basic 32-bit integer instruction set of RISC-V, which is de…
A portable and Linux capable RISC-V computer system in Verilog HDL
Junya Miura, Hiromu Miyazaki, Kenji Kise
RISC-V is an open and royalty free instruction set architecture which has been developed at the University of California, Berkeley. The processors using RISC-V can be designed and…
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining
Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam +1
RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basi…