activity
20182024
most citedAn Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors

34 citations · 71 across the 10 of their papers we have counts for

collaborators

11 papers

cs.CR2024★ 4 cited

VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Anna Lena Duque Antón, Johannes Müller, Philipp Schmitz +6

Protecting data in memory from attackers continues to be a concern in computing systems. CHERI is a promising approach to achieve such protection, by providing and enforcing fine-g…

cs.CR2023★ 2 cited

A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators

Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann +3

The threat of hardware Trojans (HTs) in security-critical IPs like cryptographic accelerators poses severe security risks. The HT detection methods available today mostly rely on g…

cs.CR2023★ 2 cited

Okapi: Efficiently Safeguarding Speculative Data Accesses in Sandboxed Environments

Philipp Schmitz, Tobias Jauch, Alex Wezel +6

This paper introduces Okapi, a new hardware/software cross-layer architecture designed to mitigate Transient Execution Side Channel attacks, including Spectre variants, in modern c…

cs.CR2023★ 1 cited

MCU-Wide Timing Side Channels and Their Detection

Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann +8

Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) or parallelism between at…

cs.CR2023★ 11 cited

A Scalable Formal Verification Methodology for Data-Oblivious Hardware

Lucas Deutschmann, Johannes Mueller, Mohammad Rahmani Fadiheh +2

The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-p…

cs.FL2022★ 5 cited

A Framework for Formal Verification of DRAM Controllers

Lukas Steiner, Chirag Sudarshan, Matthias Jung +2

The large number of recent JEDEC DRAM standard releases and their increasing feature set makes it difficult for designers to rapidly upgrade the memory controller IPs to each new s…