18 citations · 62 across the 10 of their papers we have counts for
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cs.PL2021★ 2 cited
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
Hanchen Ye, Cong Hao, Jianyi Cheng +4
High-level synthesis (HLS) has been widely adopted as it significantly improves the hardware design productivity and enables efficient design space exploration (DSE). Existing HLS…
cs.AR2021★ 2 cited
Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment
Xiaofan Zhang, Hanchen Ye, Deming Chen
Customized hardware accelerators have been developed to provide improved performance and efficiency for DNN inference and training. However, the existing hardware accelerators may…