2 papers
cs.DC2020
HyperLogLog Sketch Acceleration on FPGA
Amit Kulkarni, Monica Chiosa, Thomas B. Preußer +3
Data sketches are a set of widely used approximated data summarizing techniques. Their fundamental property is sub-linear memory complexity on the input cardinality, an important a…
cs.AR2020
Using DSP Slices as Content-Addressable Update Queues
Thomas B. Preußer, Monica Chiosa, Alexander Weiss +1
Content-Addressable Memory (CAM) is a powerful abstraction for building memory caches, routing tables and hazard detection logic. Without a native CAM structure available on FPGA d…