4 citations · 13 across the 7 of their papers we have counts for
8 papers
Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis
Pantea Kiaei, Yuan Yao, Zhenyuan Liu +7
While side-channel leakage is traditionally evaluated from a fabricated chip, it is more time-efficient and cost-effective to do so during the design phase of the chip. We present…
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
Pantea Kiaei, Zhenyuan Liu, Patrick Schaumont
Pre-silicon side-channel leakage assessment is a useful tool to identify hardware vulnerabilities at design time, but it requires many high-resolution power traces and increases th…
Dimming Down LED: An Open-source Threshold Implementation on Light Encryption Device (LED) Block Cipher
Yuan Yao, Mo Yang, Pantea Kiaei +1
Lightweight block ciphers have been widely used in applications such as RFID tags, IoTs, and network sensors. Among them, with comparable parameters, the Light Encryption Device (L…
Real-time Detection and Adaptive Mitigation of Power-based Side-Channel Leakage in SoC
Pantea Kiaei, Yuan Yao, Patrick Schaumont
Power-based side-channel is a serious security threat to the System on Chip (SoC). The secret information is leaked from the power profile of the system while a cryptographic algor…
Programmable RO (PRO): A Multipurpose Countermeasure against Side-channel and Fault Injection Attack
Yuan Yao, Pantea Kiaei, Richa Singh +2
Side-channel and fault injection attacks reveal secret information by monitoring or manipulating the physical effects of computations involving secret variables. Circuit-level coun…
SN4KE: Practical Mutation Testing at Binary Level
Mohsen Ahmadi, Pantea Kiaei, Navid Emamdoost
Mutation analysis is an effective technique to evaluate a test suite adequacy in terms of revealing unforeseen bugs in software. Traditional source- or IR-level mutation analysis i…