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20142021
most citedA Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug

4 citations · 6 across the 5 of their papers we have counts for

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cs.LO2014★ 1 cited

Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis

Disha Puri, Sandip Ray, Kecheng Hao +1

Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its Register-Transfer Level (RTL) implementation. Loop pipelining is one of the most critical a…