activity
20182024
most citedA 0.086-mm 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

331 citations · 904 across the 11 of their papers we have counts for

collaborators

12 papers

cs.AR2024★ 9 cited

A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11-m Bulk and 22-nm FD-SOI

Martin Lefebvre, David Bol

In recent years, the development of the Internet of Things (IoT) has prompted the search for nA-range current references that are simultaneously constrained to a small area and rob…

cs.AR2024★ 7 cited

A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11-m Bulk and 22-nm FD-SOI

Martin Lefebvre, David Bol

Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT s…

cs.AR2023★ 11 cited

A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI

Martin Lefebvre, Denis Flandre, David Bol

In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However…

cs.AR2022★ 24 cited

A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-m with 0.1-nA PTAT and 1.1-A CWT 38-ppm/C Designs

Martin Lefebvre, David Bol

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions.…

eess.SP2021

Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller

Mathieu Xhonneux, Jérôme Louveaux, David Bol

Emerging Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consis…

cs.NE2021★ 101 cited

Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligence

Charlotte Frenkel, David Bol, Giacomo Indiveri

While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is t…

cs.CY2021★ 100 cited

Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach

Thibault Pirson, David Bol

In upcoming years, the number of Internet-of-Things (IoT) devices is expected to surge up to tens of billions of physical objects. However, while the IoT is often presented as a pr…

cs.NE2020

A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas

Charlotte Frenkel, Jean-Didier Legat, David Bol

In an attempt to follow biological information representation and organization principles, the field of neuromorphic engineering is usually approached bottom-up, from the biophysic…

eess.SP2019★ 69 cited

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

Mathieu Xhonneux, Orion Afisiadis, David Bol +1

LoRaWAN is nowadays one of the most popular protocols for low-power Internet-of-Things communications. Although its physical layer, namely LoRa, has been thoroughly studied in the…

stat.ML2019★ 76 cited

Learning without feedback: Fixed random learning signals allow for feedforward training of deep neural networks

Charlotte Frenkel, Martin Lefebvre, David Bol

While the backpropagation of error algorithm enables deep neural network training, it implies (i) bidirectional synaptic weight transport and (ii) update locking until the forward…

cs.NE2019★ 176 cited

MorphIC: A 65-nm 738k-Synapse/mm Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Charlotte Frenkel, Jean-Didier Legat, David Bol

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-…

cs.ET2018★ 331 cited

A 0.086-mm 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat +1

Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications…