From the 1 of 5 linked papers with an AI index.
31 citations · 31 across the 1 of their papers we have counts for
5 papers
Improving Autonomous Nano-drones Performance via Automated End-to-End Optimization and Deployment of DNNs
Vlad Niculescu, Lorenzo Lamberti, Francesco Conti +2
The paper presents an automated workflow to train, optimize, and deploy a vision-based CNN (PULP‑Dronet) on an ultra‑low‑power multicore SoC for autonomous navigation of sub‑10 cm…
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System
Lorenzo Lamberti, Manuele Rusci, Marco Fariselli +2
In this paper, we present the first (to the best of our knowledge) demonstration of a low-power MCU-based edge device for Automatic License Plate Recognition (ALPR). The design lev…
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak +2
Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental security assumptions. They leverage timing variations of sever…
A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi +19
Recent trends in deep learning (DL) have made hardware accelerators essential for various high-performance computing (HPC) applications, including image classification, computer vi…
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Matteo Perotti, Matheus Cavalcante, Nils Wistoff +3
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips,…