11 citations · 21 across the 3 of their papers we have counts for
3 papers
cs.ET2021
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor
Chi-Shuen Lee, Brian Cline, Saurabh Sinha +2
We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characteriz…
cs.AR2020★ 10 cited
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling
Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava +3
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D…
cs.AR2018★ 11 cited
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK
Xiaoqing Xu, Nishi Shah, Andrew Evans +3
Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and…