73 citations · 93 across the 6 of their papers we have counts for
6 papers
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Abdullah Giray Yağlıkçı, Ataberk Olgun, Minesh Patel +5
DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interferi…
A Case for Transparent Reliability in DRAM Systems
Minesh Patel, Taha Shahroodi, Aditya Manglik +4
Today's systems have diverse needs that are difficult to address using one-size-fits-all commodity DRAM. Unfortunately, although system designers can theoretically adapt commodity…
A Deeper Look into RowHammer`s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
Lois Orosa, Abdullah Giray Yağlıkçı, Haocong Luo +6
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer vulnerability w…
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati +10
DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM exec…
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
Ataberk Olgun, Minesh Patel, A. Giray Yağlıkçı +6
True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic pri…
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
Haocong Luo, Taha Shahroodi, Hasan Hassan +5
DRAM is the prevalent main memory technology, but its long access latency can limit the performance of many workloads. Although prior works provide DRAM designs that reduce DRAM ac…