100 citations · 198 across the 14 of their papers we have counts for
14 papers
PerfReasoning: How Well Do LLMs Reason on Hardware Performance?
Dan Zhao, Karthikeyan Sankaralingam, Christos Kozyrakis +1
Performance modeling is central to hardware design and software optimization, yet constructing these models requires structured reasoning about computation, data reuse, storage, an…
SOL-ExecBench: Speed-of-Light Benchmarking for Real-World GPU Kernels Against Hardware Limits
Edward Lin, Sahil Modi, Siva Kumar Sastry Hari +30
As agentic AI systems become increasingly capable of generating and optimizing GPU kernels, progress is constrained by benchmarks that reward speedup over software baselines rather…
High-Throughput SAT Sampling
Arash Ardakani, Minwoo Kang, Kevin He +2
In this work, we present a novel technique for GPU-accelerated Boolean satisfiability (SAT) sampling. Unlike conventional sampling algorithms that directly operate on conjunctive n…
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
Arash Ardakani, Minwoo Kang, Kevin He +4
Efficient sampling of satisfying formulas for circuit satisfiability (CircuitSAT), a well-known NP-complete problem, is essential in modern front-end applications for thorough test…
Full Stack Optimization of Transformer Inference: a Survey
Sehoon Kim, Coleman Hooper, Thanakul Wattanawong +9
Recent advances in state-of-the-art DNN architecture design have been moving toward Transformer models. These models achieve superior accuracy across a wide range of applications.…
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Qijing Huang, Minwoo Kang, Grace Dinh +5
Recent advances in Deep Neural Networks (DNNs) have led to active development of specialized DNN accelerators, many of which feature a large number of processing elements laid out…
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Zhen Dong, Yizhao Gao, Qijing Huang +3
Automatic algorithm-hardware co-design for DNN has shown great success in improving the performance of DNNs on FPGAs. However, this process remains challenging due to the intractab…
HAWQV3: Dyadic Neural Network Quantization
Zhewei Yao, Zhen Dong, Zhangcheng Zheng +8
Current low-precision quantization algorithms often have the hidden cost of conversion back and forth from floating point to quantized integer values. This hidden cost limits the l…
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs
Zhen Dong, Dequan Wang, Qijing Huang +6
Deploying deep learning models on embedded systems has been challenging due to limited computing resources. The majority of existing work focuses on accelerating image classificati…
ProTuner: Tuning Programs with Monte Carlo Tree Search
Ameer Haj-Ali, Hasan Genc, Qijing Huang +4
We explore applying the Monte Carlo Tree Search (MCTS) algorithm in a notoriously difficult task: tuning programs for high-performance deep learning and image processing. We build…
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
Qijing Huang, Ameer Haj-Ali, William Moses +4
The performance of the code a compiler generates depends on the order in which it applies the optimization passes. Choosing a good order--often referred to as the phase-ordering pr…
Algorithm-hardware Co-design for Deformable Convolution
Qijing Huang, Dequan Wang, Yizhao Gao +5
FPGAs provide a flexible and efficient platform to accelerate rapidly-changing algorithms for computer vision. The majority of existing work focuses on accelerating image classific…
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
Ameer Haj-Ali, Qijing Huang, William Moses +4
The performance of the code generated by a compiler depends on the order in which the optimization passes are applied. In high-level synthesis, the quality of the generated circuit…
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
Yifan Yang, Qijing Huang, Bichen Wu +8
Using FPGAs to accelerate ConvNets has attracted significant attention in recent years. However, FPGA accelerator design has not leveraged the latest progress of ConvNets. As a res…