2 papers
cs.PL2025
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
Yiyao Yang, Fu Teng, Pengju Liu +5
Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works ha…
cs.ET2024
High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling
Xingyue Qian, Chenyang Lv, Zhezhi He +1
In-memory computing (IMC) with single instruction multiple data (SIMD) setup enables memory to perform operations on the stored data in parallel to achieve high throughput and ener…