activity
20152023
most citeduops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures

76 citations · 157 across the 11 of their papers we have counts for

collaborators

14 papers

cs.PL2023

Leveraging LLVM's ScalarEvolution for Symbolic Data Cache Analysis

Valentin Touzeau, Jan Reineke

While instruction cache analysis is essentially a solved problem, data cache analysis is more challenging. In contrast to instruction fetches, the data accesses generated by a memo…

cs.CR2023★ 3 cited

Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts

Zilong Wang, Gideon Mohr, Klaus von Gleissenthall +2

Leakage contracts have recently been proposed as a new security abstraction at the Instruction Set Architecture (ISA) level. Such contracts aim to faithfully capture the informatio…

cs.PL2022

Warping Cache Simulation of Polyhedral Programs

Canberk Morelli, Jan Reineke

Techniques to evaluate a program's cache performance fall into two camps: 1. Traditional trace-based cache simulators precisely account for sophisticated real-world cache models an…

cs.PF2021★ 27 cited

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures

Andreas Abel, Jan Reineke

Performance models that statically predict the steady-state throughput of basic blocks on particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide o…

cs.CR2020

Hardware-Software Contracts for Secure Speculation

Marco Guarnieri, Boris Köpf, Jan Reineke +1

Since the discovery of Spectre, a large number of hardware mechanisms for secure speculation has been proposed. Intuitively, more defensive mechanisms are less efficient but can se…

cs.CR2020★ 3 cited

Flushgeist: Cache Leaks from Beyond the Flush

Pepe Vila, Andreas Abel, Marco Guarnieri +2

Flushing the cache, using instructions like clflush and wbinvd, is commonly proposed as a countermeasure against access-based cache attacks. In this report, we show that several In…

cs.PF2019★ 44 cited

nanoBench: A Low-Overhead Tool for Running Microbenchmarks on x86 Systems

Andreas Abel, Jan Reineke

We present nanoBench, a tool for evaluating small microbenchmarks using hardware performance counters on Intel and AMD x86 systems. Most existing tools and libraries are intended t…

cs.PL2019★ 1 cited

Cache Persistence Analysis: Finally Exact

Gregory Stock, Sebastian Hahn, Jan Reineke

Cache persistence analysis is an important part of worst-case execution time (WCET) analysis. It has been extensively studied in the past twenty years. Despite these efforts, all e…

cs.PL2018

Fast and exact analysis for LRU caches

Claire Maïza, Valentin Touzeau, David Monniaux +1

For applications in worst-case execution time analysis and in security, it is desirable to statically classify memory accesses into those that result in cache hits, and those that…

cs.CR2018

SPECTECTOR: Principled Detection of Speculative Information Flows

Marco Guarnieri, Boris Köpf, José F. Morales +2

Since the advent of SPECTRE, a number of countermeasures have been proposed and deployed. Rigorously reasoning about their effectiveness, however, requires a well-defined notion of…

cs.PF2018★ 76 cited

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures

Andreas Abel, Jan Reineke

Modern microarchitectures are some of the world's most complex man-made systems. As a consequence, it is increasingly difficult to predict, explain, let alone optimize the performa…

cs.CR2018★ 3 cited

On the Incomparability of Cache Algorithms in Terms of Timing Leakage

Pablo Cañones, Boris Köpf, Jan Reineke

Modern computer architectures rely on caches to reduce the latency gap between the CPU and main memory. While indispensable for performance, caches pose a serious threat to securit…

cs.CR2017

Security Analysis of Cache Replacement Policies

Pablo Cañones, Boris Köpf, Jan Reineke

Modern computer architectures share physical resources between different programs in order to increase area-, energy-, and cost-efficiency. Unfortunately, sharing often gives rise…

cs.DS2015

On the Smoothness of Paging Algorithms

Jan Reineke, Alejandro Salinger

We study the smoothness of paging algorithms. How much can the number of page faults increase due to a perturbation of the request sequence? We call a paging algorithm smooth if th…