2 citations · 2 across the 3 of their papers we have counts for
4 papers · 1 filter
Task-Graph Scheduling Extensions for Efficient Synchronization and Communication
Seonmyeong Bak, Oscar Hernandez, Mark Gates +2
Task graphs have been studied for decades as a foundation for scheduling irregular parallel applications and incorporated in programming models such as OpenMP. While many high-perf…
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine
Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss +2
Xilinx's AI Engine is a recent industry example of energy-efficient vector processing that includes novel support for 2D SIMD datapaths and shuffle interconnection network. The cur…
Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators
Prasanth Chatarasi, Hyoukjun Kwon, Natesh Raina +6
The efficiency of a spatial DNN accelerator depends heavily on the compiler and its cost model ability to generate optimized mappings for various operators of DNN models on to the…
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer +3
The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact the performance and e…