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researcher

G. Hellings

2 papers hereh-index 7144 citations44 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author1
  • last author1

Across the 2 of 2 papers where every author was matched, so the position is known.

fields
  • cs.ET1
  • physics.app-ph1

identity via Semantic Scholar / OpenAlex

works on
2d semiconductors 1a2 node 1cfet scaling 1device architecture 1gate-all-around transistors 1

From the 1 of 2 linked papers with an AI index.

collaborators

2 papers

physics.app-ph2026

Are gate-all-around 2D CFETs the optimal architecture for the A2 node and beyond?

Fengben Xi, Gautam Gaddemane, Anshul Gupta +15

The paper investigates whether gate‑all‑around (GAA) 2D complementary field‑effect transistors (CFETs) can outperform silicon GAA CFETs at the A2 technology node, presenting an int…

cs.ET2025

SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study

Yang Xiang, Fernando García-Redondo, Arvind Sharma +9

This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-…

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